Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7754559 | Method for fabricating capacitor structures using the first contact metal | Yakov Roizin, Alexey Heiman, Michael Lisiansky, Amos Fenigstein, Myriam Buchbinder | 2010-07-13 |
| 7700994 | Single poly CMOS logic memory cell for RFID application and its programming and erasing method | Yakov Roizin, Evgeny Pikhay, Adi Birman, Daniel Nehmad | 2010-04-20 |
| 7439575 | Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories | Yakov Roizin, Micha Gutman, Menachem Vofsy, Avi Ben-Gigi | 2008-10-21 |
| 7060627 | Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays | Micha Gutman, Yakov Roizin, Menachem Vofsy, Avi Ben-Gigi, Fumihiko Noro +3 more | 2006-06-13 |
| 6959920 | Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories | Yakov Roizin, Micha Gutman, Menachem Vofsy, Avi Ben-Gigi | 2005-11-01 |
| 6703298 | Self-aligned process for fabricating memory cells with two isolated floating gates | Yakov Roizin, Ruth Shima-Edelstein, Christopher M. Cork | 2004-03-09 |
| 6686276 | Semiconductor chip having both polycide and salicide gates and methods for making same | Itzhak Edrei | 2004-02-03 |
| 6583066 | Methods for fabricating a semiconductor chip having CMOS devices and fieldless array | Shai Kfir, Menchem Vofsy, Avi Ben-Guioui | 2003-06-24 |
| 6458702 | Methods for making semiconductor chip having both self aligned silicide regions and non-self aligned silicide regions | — | 2002-10-01 |
| 6346442 | Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array | Shai Kfir, Menchem Vofsy, Avi Ben-Guigui | 2002-02-12 |