Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10185793 | Conditional-based duration logic | Srinath Avadhanula, Yit Phang Khoo | 2019-01-22 |
| 9507888 | Active state visualization for finite state machine models | Nishith Aggarwal, Srinath Avadhanula, Vijaya Raghavan | 2016-11-29 |
| 9003357 | Code generation for querying an active state of a model | Srinath Avadhanula | 2015-04-07 |