Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9715911 | Nonvolatile backup of a machine state when a power supply drops below a threshhold | Steven Craig Bartling | 2017-07-25 |
| 9711196 | Configuration bit sequencing control of nonvolatile domain and array wakeup and backup | Steven Craig Bartling | 2017-07-18 |
| 9520862 | Dual-port negative level sensitive reset preset data retention latch | Steven Craig Bartling | 2016-12-13 |
| 9520863 | Dual-port negative level sensitive preset data retention latch | Steven Craig Bartling | 2016-12-13 |
| 9454437 | Non-volatile logic based processing device | Andreas Waechter, Mark Jung, Steven Craig Bartling | 2016-09-27 |
| 9342259 | Nonvolatile logic array and power domain segmentation in processing device | Steven Craig Bartling | 2016-05-17 |
| 9335954 | Customizable backup and restore from nonvolatile logic array | Steven Craig Bartling | 2016-05-10 |
| 9270257 | Dual-port positive level sensitive reset data retention latch | Steven Craig Bartling | 2016-02-23 |
| 9160314 | Negative edge flip-flop with dual-port slave latch | Steven Craig Bartling | 2015-10-13 |
| 9099998 | Positive edge preset reset flip-flop with dual-port slave latch | Steven Craig Bartling | 2015-08-04 |
| 9088271 | Dual-port positive level sensitive data retention latch | Steven Craig Bartling | 2015-07-21 |
| 9083328 | Positive edge flip-flop with dual-port slave latch | Steven Craig Bartling | 2015-07-14 |
| 9058126 | Nonvolatile logic array with retention flip flops to reduce switching power during wakeup | Steven Craig Bartling | 2015-06-16 |
| 9018976 | Dual-port positive level sensitive reset preset data retention latch | Steven Craig Bartling | 2015-04-28 |
| 9013218 | Dual-port negative level sensitive reset data retention latch | Steven Craig Bartling | 2015-04-21 |
| 9013217 | Dual-port negative level sensitive data retention latch | Steven Craig Bartling | 2015-04-21 |
| 9007091 | Dual-port positive level sensitive preset data retention latch | Steven Craig Bartling | 2015-04-14 |
| 9007111 | Negative edge reset flip-flop with dual-port slave latch | Steven Craig Bartling | 2015-04-14 |
| 8897088 | Nonvolatile logic array with built-in test result signal | Steven Craig Bartling | 2014-11-25 |
| 8854858 | Signal level conversion in nonvolatile bitcell array | Steven Craig Bartling | 2014-10-07 |
| 8854079 | Error detection in nonvolatile logic arrays using parity | Steven Craig Bartling | 2014-10-07 |
| 8836398 | Negative edge flip-flop with dual-port slave latch | Steven Craig Bartling | 2014-09-16 |
| 8836399 | Positive edge flip-flop with dual-port slave latch | Steven Craig Bartling | 2014-09-16 |
| 8836400 | Positive edge preset flip-flop with dual-port slave latch | Steven Craig Bartling | 2014-09-16 |
| 8829963 | Negative edge preset reset flip-flop with dual-port slave latch | Steven Craig Bartling | 2014-09-09 |