Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12196587 | Gas volume determination in fluid | Anand G. Dabak | 2025-01-14 |
| 11847427 | Load store circuit with dedicated single or dual bit shift circuit and opcodes for low power accelerator processor | Seok-Jun Lee | 2023-12-19 |
| 11725967 | Gas volume determination in fluid | Anand G. Dabak | 2023-08-15 |
| 11502951 | Network communication system with node energy reduction packet protocol | Tarkesh Pande | 2022-11-15 |
| 11353347 | Ultrasonic flow meter and excitation method | Anand G. Dabak, Luis Reynoso Covarrubias, Srinath Ramaswamy | 2022-06-07 |
| 11341085 | Low energy accelerator processor architecture with short parallel instruction word | Seok-Jun Lee, Johann Zipperer, Manish Goel | 2022-05-24 |
| 10740280 | Low energy accelerator processor architecture with short parallel instruction word | Seok-Jun Lee, Johann Zipperer, Manish Goel | 2020-08-11 |
| 10693778 | Network communication system with node energy reduction packet protocol | Tarkesh Pande | 2020-06-23 |
| 10656914 | Methods and instructions for a 32-bit arithmetic support using 16-bit multiply and 32-bit addition | Seok-Jun Lee, Manish Goel | 2020-05-19 |
| 10503474 | Methods and instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition | Seok-Jun Lee, Manish Goel | 2019-12-10 |
| 10241791 | Low energy accelerator processor architecture | Seok-Jun Lee, Johann Zipperer, Manish Goel | 2019-03-26 |
| 10050878 | Network communication system with node energy reduction packet protocol | Tarkesh Pande | 2018-08-14 |
| 9952865 | Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file | Seok-Jun Lee, Johann Zipperer, Manish Goel | 2018-04-24 |
| 9954514 | Output range for interpolation architectures employing a cascaded integrator-comb (CIC) filter with a multiplier | Tarkesh Pande | 2018-04-24 |
| 9935681 | Preamble sequence detection of direct sequence spread spectrum (DSSS) signals | Timothy M. Schmidl | 2018-04-03 |
| 9817791 | Low energy accelerator processor architecture with short parallel instruction word | Seok-Jun Lee, Johann Zipperer, Manish Goel | 2017-11-14 |
| 9276636 | Adaptive modulation system and method to minimize energy consumption | Tarkesh Pande | 2016-03-01 |
| 9231648 | Methods and apparatus for frequency offset estimation and correction prior to preamble detection of direct sequence spread spectrum (DSSS) signals | Timothy M. Schmidl | 2016-01-05 |
| 8755675 | Flexible and efficient memory utilization for high bandwidth receivers, integrated circuits, systems, methods and processes of manufacture | Michael DiRenzo, Assaf Sella, Manish Goel | 2014-06-17 |
| 8705336 | Delayed data feeding for increased media access control processing time | Jin-Meng Ho, Anuj Batra | 2014-04-22 |
| 8601269 | Methods and systems for close proximity wireless communications | Anuj Batra | 2013-12-03 |
| 8102187 | Localized calibration of programmable digital logic cells | Anuj Batra, Kit Wing S. Lee, Clive Bittlestone, Ekanayake A. Amerasekera | 2012-01-24 |
| 8099658 | Reduced complexity Viterbi decoder | Seok-Jun Lee, Anuj Batra, Manish Goel | 2012-01-17 |
| 7973557 | IC having programmable digital logic cells | Clive Bittlestone, Kit Wing S. Lee, Ekanayake A. Amerasekera, Anuj Batra | 2011-07-05 |
| 7957760 | Method and apparatus for transmit power control in wireless data communications systems | Anuj Batra | 2011-06-07 |