Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11018071 | Initiation of one or more processors in an integrated circuit | — | 2021-05-25 |
| 7487379 | High performance integrated circuit with low skew clocking networks and improved low power operating mode having reduced recovery time | Hai Ngoc Nguyen, Yuanping Chen | 2009-02-03 |
| 6518945 | Replacing defective circuit elements by column and row shifting in a flat-panel display | — | 2003-02-11 |
| 6288712 | System and method for reducing peak current and bandwidth requirements in a display driver circuit | W. Spencer Worley, III, Edwin Lyle Hudson, John G. Campbell | 2001-09-11 |
| 6072452 | System and method for using forced states to improve gray scale performance of a display | W. Spencer Worley, III | 2000-06-06 |
| 5661692 | Read/write dual port memory having an on-chip input data register | Anthony M. Balistreri | 1997-08-26 |
| 5590083 | Process of writing data from a data processor to a memory device register that is separate from the array | Anthony M. Balistreri | 1996-12-31 |
| 5528551 | Read/write memory with plural memory cell write capability at a selected row address | — | 1996-06-18 |
| 5508960 | Read/write memory with selective row write capability | — | 1996-04-16 |
| 5434969 | Video display system using memory with a register arranged to present an entire pixel at once to the display | Andrew L. Heilveil, Jerry R. VanAken, Karl M. Guttag, Donald J. Redwine, Mark F. Novak | 1995-07-18 |
| 5210639 | Dual-port memory with inhibited random access during transfer cycles with serial access | Donald J. Redwine | 1993-05-11 |
| 5195056 | Read/write memory having an on-chip input data register, having pointer circuits between a serial data register and input/output buffer circuits | Anthony M. Balistreri | 1993-03-16 |
| 5163024 | Video display system using memory with parallel and serial access employing serial shift registers selected by column address | Andrew L. Heilveil, Jerry R. VanAken, Karl M. Guttag, Donald J. Redwine, Mark F. Novak | 1992-11-10 |
| 5042014 | Dual-port memory having pipelined serial output | Daniel F. Anderson | 1991-08-20 |
| 4961171 | Read/write memory having an on-chip input data register | Anthony M. Balistreri | 1990-10-02 |
| 4897818 | Dual-port memory with inhibited random access during transfer cycles | Donald J. Redwine | 1990-01-30 |
| 4891795 | Dual-port memory having pipelined serial output | Daniel F. Anderson | 1990-01-02 |
| 4866678 | Dual-port memory having pipelined serial output | Daniel F. Anderson | 1989-09-12 |
| 4817058 | Multiple input/output read/write memory having a multiple-cycle write mask | — | 1989-03-28 |
| 4807189 | Read/write memory having a multiple column select mode | Anthony M. Balistreri | 1989-02-21 |
| 4796231 | Serial accessed semiconductor memory with reconfigurable shift registers | — | 1989-01-03 |
| 4747081 | Video display system using memory with parallel and serial access employing serial shift registers selected by column address | Andrew L. Heilveil, Jerry R. VanAken, Karl M. Guttag, Donald J. Redwine, Mark F. Novak | 1988-05-24 |
| 4720819 | Method and apparatus for clearing the memory of a video computer | Karl M. Guttag | 1988-01-19 |
| 4689741 | Video system having a dual-port memory with inhibited random access during transfer cycles | Donald J. Redwine | 1987-08-25 |
| 4683555 | Serial accessed semiconductor memory with reconfigureable shift registers | — | 1987-07-28 |