Issued Patents All Time
Showing 26–50 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6624678 | Schmitt trigger device with disable | Sean Fitzpatrick, Paul D. Krivacek | 2003-09-23 |
| 6624682 | Method and an apparatus to actively sink current in an integrated circuit with a floating I/O supply voltage | Sean Fitzpatrick, Paul D. Krivacek | 2003-09-23 |
| 6600345 | Glitch free clock select switch | — | 2003-07-29 |
| 6438720 | Host port interface | Jason A. T. Jones, Marc Couvrat, Oliver Mougenot, Mansoor A. Chishtie | 2002-08-20 |
| 6334181 | DSP with wait state registers having at least two portions | Peter N. Ehlig | 2001-12-25 |
| 6311264 | Digital signal processor with wait state register | Peter N. Ehlig | 2001-10-30 |
| 6263419 | Integrated circuit with wait state registers | Peter N. Ehlig | 2001-07-17 |
| 6263418 | Process of operating a microprocessor to use wait state numbers | Peter N. Ehlig | 2001-07-17 |
| 6253307 | Data processing device with mask and status bits for selecting a set of status conditions | Peter N. Ehlig | 2001-06-26 |
| 6249859 | IC with wait state registers | Peter N. Ehlig | 2001-06-19 |
| 6249860 | System with wait state registers | Peter N. Ehlig | 2001-06-19 |
| 6247111 | System with wait state register | Peter N. Ehlig | 2001-06-12 |
| 6243801 | System with wait state registers | Peter N. Ehlig | 2001-06-05 |
| 6240504 | Process of operating a microprocessor to change wait states | Peter N Ehlig | 2001-05-29 |
| 6240505 | System with wait state registers | Peter N. Ehlig | 2001-05-29 |
| 6134578 | Data processing device and method of operation with context switching | Peter N. Ehlig, James F. Hollander | 2000-10-17 |
| 6038649 | Address generating circuit for block repeat addressing for a pipelined processor | Yuji Ozawa, Shigeshi Abiko | 2000-03-14 |
| 5946483 | Devices, systems and methods for conditional instructions | Peter N. Ehlig | 1999-08-31 |
| 5907714 | Method for pipelined data processing with conditioning instructions for controlling execution of instructions without pipeline flushing | Peter N. Ehlig | 1999-05-25 |
| 5838934 | Host port interface | Jason A. T. Jones, Marc Couvrat, Oliver Mougenot, Mansoor A. Chishtie | 1998-11-17 |
| 5787481 | System for managing write and/or read access priorities between central processor and memory operationally connected | Sigheshi Abiko | 1998-07-28 |
| 5765218 | Address generating circuit for generating addresses separated by a prescribed step value in circular addressing | Yuji Ozawa, Shigeshi Abiko | 1998-06-09 |
| 5734927 | System having registers for receiving data, registers for transmitting data, both at a different clock rate, and control circuitry for shifting the different clock rates | Marc Couvrat, Yves Masse, Mansoor A. Chishtie, Alain Vallauri, Ajay Padgaonkar +1 more | 1998-03-31 |
| 5652910 | Devices and systems with conditional instructions | Peter N. Ehlig | 1997-07-29 |
| 5617574 | Devices, systems and methods for conditional instructions | Peter N. Ehlig | 1997-04-01 |