AS

Andreas Steininger

TW Technische Universität Wien: 1 patents #75 of 329Top 25%
📍 Wien, AT: #1,767 of 3,624 inventorsTop 50%
Overall (All Time): #3,301,877 of 4,157,543Top 80%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7791394 Decentralised fault-tolerant clock pulse generation in VLSI chips Ulrich Schmid 2010-09-07