Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11615494 | Intellectual property recommending method and system | Hsiao-Han Hu, Tai-Chuan Chen | 2023-03-28 |
| 8943453 | Automatic application-rule checker | Shien-Po Yang, Vincent Merigot | 2015-01-27 |
| 8501622 | Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof | — | 2013-08-06 |
| 8492795 | Integrated circuit having input/output cell array having single gate orientation | — | 2013-07-23 |
| 7884643 | Low leakage voltage level shifting circuit | Guang-Cheng Wang, Kuo-Ji Chen | 2011-02-08 |
| 7865852 | Method for automatically routing multi-voltage multi-pitch metal lines | — | 2011-01-04 |
| 7795939 | Method and system for setup/hold characterization in sequential cells | Ching-Hao Shaw | 2010-09-14 |
| 7714362 | Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof | — | 2010-05-11 |
| 7649214 | ESD protection system for multiple-domain integrated circuits | — | 2010-01-19 |
| 7594198 | Ultra fine pitch I/O design for microchips | — | 2009-09-22 |
| 7557413 | Serpentine ballasting resistors for multi-finger ESD protection device | — | 2009-07-07 |
| 7500214 | System and method for reducing design cycle time for designing input/output cells | Ming-Hsiang Song, Chang-Fen Hu | 2009-03-03 |
| 7420789 | ESD protection system for multi-power domain circuitry | — | 2008-09-02 |
| 7417837 | ESD protection system for multi-power domain circuitry | — | 2008-08-26 |
| 7362136 | Dual voltage single gate oxide I/O circuit with high voltage stress tolerance | — | 2008-04-22 |
| 7330702 | Method and apparatus for inter-chip wireless communication | Tsung-Yang Hung | 2008-02-12 |
| 7295052 | Regenerative power-on control circuit | — | 2007-11-13 |
| 7274544 | Gate-coupled ESD protection circuit for high voltage tolerant I/O | Cheng-Ming Chiang | 2007-09-25 |
| 7248076 | Dual-voltage three-state buffer circuit with simplified tri-state level shifter | Kuo-Ji Chen | 2007-07-24 |
| 7221183 | Tie-high and tie-low circuit | — | 2007-05-22 |
| 7221551 | Cascaded gate-driven ESD clamp | — | 2007-05-22 |
| 7193441 | Single gate oxide I/O buffer with improved under-drive feature | Kuo-Ji Chen | 2007-03-20 |
| 7173472 | Input buffer structure with single gate oxide | Kuo-Ji Chen, Tsung-Hsin Yu | 2007-02-06 |
| 7168021 | Built-in test circuit for an integrated circuit device | — | 2007-01-23 |
| 7151400 | Boost-biased level shifter | — | 2006-12-19 |