Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12197131 | Method for reducing line-end space in integrated circuit patterning | Ya-Wen Chiu, Lun-Kuang Tan | 2025-01-14 |
| 11908740 | Semiconductor structure with doped via plug | Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jie Huang, Lun-Kuang Tan +3 more | 2024-02-20 |
| 11635695 | Method for reducing line-end space in integrated circuit patterning | Ya-Wen Chiu, Lun-Kuang Tan | 2023-04-25 |
| 11532485 | Process for making multi-gate transistors and resulting structures | Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Lun-Kuang Tan, Huicheng Chang | 2022-12-20 |
| 11515206 | Semiconductor structure with doped via plug | Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jie Huang, Lun-Kuang Tan +3 more | 2022-11-29 |
| 10854471 | Process for making multi-gate transistors and resulting structures | Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Lun-Kuang Tan, Huicheng Chang | 2020-12-01 |
| 10763168 | Semiconductor structure with doped via plug and method for forming the same | Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jie Huang, Lun-Kuang Tan +3 more | 2020-09-01 |
| 10700181 | Fin field effect transistor (finFET) device structure and method for forming the same | Wei Huang, Wen-Yen Chen | 2020-06-30 |
| 10361094 | Process for making multi-gate transistors and resulting structures | Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Lun-Kuang Tan, Huicheng Chang | 2019-07-23 |
| 10177006 | Process for making multi-gate transistors and resulting structures | Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Lun-Kuang Tan, Huicheng Chang | 2019-01-08 |