Issued Patents All Time
Showing 76–100 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7275233 | Methods and apparatuses for designing integrated circuits | Robert Erickson | 2007-09-25 |
| 7263673 | Method and apparatus for automated synthesis and optimization of datapaths | David Rickel | 2007-08-28 |
| 7251800 | Method and apparatus for automated circuit design | Andrew Crews, Champaka Ramachandran | 2007-07-31 |
| 7240303 | Hardware/software co-debugging in a hardware description language | Nils Endric Schubert, John Mark Beardslee, Mario Larouche | 2007-07-03 |
| 7237214 | Method and apparatus for circuit partitioning and trace assignment in circuit design | Awartika Pandey, Drazen Borkovic | 2007-06-26 |
| 7200822 | Circuits with modular redundancy and methods and apparatuses for their automated synthesis | — | 2007-04-03 |
| 7178118 | Method and apparatus for automated circuit design | Champaka Ramachandran, Andrew Crews | 2007-02-13 |
| 7146589 | Reducing equivalence checking complexity using inverse function | Jérôme Rampon | 2006-12-05 |
| 7131078 | Method and apparatus for circuit design and synthesis | Naresh Maheshwari | 2006-10-31 |
| 7117463 | Verification of digital circuitry using range generators | Robert M. Graham | 2006-10-03 |
| 7093204 | Method and apparatus for automated synthesis of multi-channel circuits | Levent Oktem | 2006-08-15 |
| 7082582 | Reducing clock skew in clock gating circuits | Drazen Borkovic | 2006-07-25 |
| 7010769 | Methods and apparatuses for designing integrated circuits | Robert Erickson | 2006-03-07 |
| 7007254 | Method and apparatus for the design and analysis of digital circuits with time division multiplexing | Drazen Borkovic | 2006-02-28 |
| 6978430 | Methods and apparatuses for designing integrated circuits | Robert Erickson | 2005-12-20 |
| 6973632 | Method and apparatus to estimate delay for logic circuit optimization | Dhananjay Brahme, Jovanka Ciric | 2005-12-06 |
| 6934183 | Method and apparatus for resetable memory and design approach for same | Vijay Seshadri | 2005-08-23 |
| 6904576 | Method and system for debugging using replicated logic | Chun Kit Ng | 2005-06-07 |
| 6836420 | Method and apparatus for resetable memory and design approach for same | Vijay Seshadri | 2004-12-28 |
| 6735743 | Method and apparatus for invalid state detection | — | 2004-05-11 |
| 6711729 | Methods and apparatuses for designing integrated circuits using automatic reallocation techniques | Smita Bakshi | 2004-03-23 |
| 6691286 | Methods and apparatuses for checking equivalence of circuits | David Rickel | 2004-02-10 |
| 6687882 | Methods and apparatuses for non-equivalence checking of circuits with subspace | Sanjeev Mahajan | 2004-02-03 |
| 6668364 | Methods and apparatuses for designing integrated circuits | Robert Erickson | 2003-12-23 |
| 6643829 | Reducing clock skew in clock gating circuits | Drazen Borkovic | 2003-11-04 |