JS

John R. Studders

SY Synopsys: 3 patents #460 of 2,302Top 20%
Overall (All Time): #1,439,746 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11132491 DRC processing tool for early stage IC layout designs 2021-09-28
10783311 DRC processing tool for early stage IC layout designs 2020-09-22
10311195 Incremental multi-patterning validation Yuli XUE, Weiping Fang, Byungwook Kim 2019-06-04