Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8731893 | Circuit simulation of MOSFETs | Mitiko Miura-Mattausch, Norio Sadachika, Shunta Kusu | 2014-05-20 |
| 7743726 | Indication instrument | — | 2010-06-29 |
| 7594206 | Fault detecting method and layout method for semiconductor integrated circuit | Reisuke Shimoda | 2009-09-22 |
| 7484166 | Semiconductor integrated circuit verification method and test pattern preparation method | Keisuke OCHI | 2009-01-27 |
| 7441168 | Fault detecting method and layout method for semiconductor integrated circuit | Reisuke Shimoda | 2008-10-21 |
| 7216315 | Error portion detecting method and layout method for semiconductor integrated circuit | — | 2007-05-08 |
| 7188326 | Methods for designing and testing semiconductor integrated circuits with plural clock groups | — | 2007-03-06 |
| 7065690 | Fault detecting method and layout method for semiconductor integrated circuit | Reisuke Shimoda | 2006-06-20 |