Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6928575 | Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture | Kazuhiro Okabayashi, Shinichi Marui | 2005-08-09 |
| 6911700 | Semiconductor integrated circuit device including digital and analog circuits comprising electrostatic destruction protection circuits | — | 2005-06-28 |
| 6879193 | Semiconductor integrated circuit and its reset method | Shinichi Marui, Kazuhiro Okabayashi | 2005-04-12 |
| 6842852 | System and method for controlling conditional branching utilizing a control instruction having a reduced word length | Masayuki Yamasaki | 2005-01-11 |
| 6754870 | CRC operation unit and CRC operation method | Takao Yoshida, Masayuki Yamasaki, Kazuhiro Okabayashi | 2004-06-22 |
| 6751773 | Coding apparatus capable of high speed operation | Kazuhiro Okabayashi, Masayuki Yamasaki | 2004-06-15 |
| 6735714 | Processing unit and processing method | Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Kevin Stone | 2004-05-11 |
| 6477661 | Processing unit and processing method | Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Kevin Stone | 2002-11-05 |
| 6450036 | Method and device for diagnosing deterioration of an article having at least a covering layer organic polymer material | Tetsuya Ashida, Tsuyoshi Ikeda, Junichiro Ikehara, Masanori Fujii, Hiroshi Ishibashi +3 more | 2002-09-17 |
| 6363469 | Address generation apparatus | Hidetoshi Suzuki | 2002-03-26 |
| 6330684 | Processor and processing method | Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Kevin Stone | 2001-12-11 |
| 6289429 | Accessing multiple memories using address conversion among multiple addresses | — | 2001-09-11 |
| 6266764 | Program controller for switching between first program and second program | — | 2001-07-24 |
| 6125153 | Data processor and data processing method | Yuji Sugisawa | 2000-09-26 |
| 5715470 | Arithmetic apparatus for carrying out viterbi decoding at a high speed | Nobuo Asano, Mitsuru Uesugi, Toshihiro Ishikawa | 1998-02-03 |
| 5537577 | Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions | Toshio Sugimura, Katsuhiko Ueda, Toshihiro Ishikawa, Mikako Yasutome | 1996-07-16 |
| 5504927 | System for controlling input/output data for an integrated one-chip microcomputer utilizing an external clock of a different speed for data transfer | Mikio Sakakibara | 1996-04-02 |