Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9823946 | Processor and program execution method capable of efficient program execution | Kazushi Kurata, Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi +5 more | 2017-11-21 |
| 9361259 | Integrated circuit with multipurpose processing and for video/audio processing optimization | Tokuzo Kiyohara, Hiroshi Mizuno, Junji MICHIYAMA, Tomohiko Kitamura, Ryoji Yamaguchi +4 more | 2016-06-07 |
| 8811470 | Integrated circuit for video/audio processing | Tokuzo Kiyohara, Hiroshi Mizuno, Junji MICHIYAMA, Tomohiko Kitamura, Ryoji Yamaguchi +4 more | 2014-08-19 |
| 8719827 | Processor and program execution method capable of efficient program execution | Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota +5 more | 2014-05-06 |
| 8082429 | Information processing apparatus and exception control circuit | Hideshi Nishida, Takeshi Furuta, Tetsuya Tanaka, Tokuzo Kiyohara | 2011-12-20 |
| 8006076 | Processor and program execution method capable of efficient program execution | Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota +5 more | 2011-08-23 |
| 7934082 | Information processing apparatus and exception control circuit | Hideshi Nishida, Takeshi Furuta, Tetsuya Tanaka, Tokuzo Kiyohara | 2011-04-26 |
| 7930520 | Processor and program execution method capable of efficient program execution | Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota +5 more | 2011-04-19 |
| 7921281 | Processor and program execution method capable of efficient program execution | Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota +5 more | 2011-04-05 |
| 7728745 | Variable length code decoding apparatus and method with variation in timing of extracting bit string to be decoded depending on code word | Yuya SHIGENOBU, Yoshiyuki Wada, Satoshi Yamaguchi, Takeshi Furuta | 2010-06-01 |
| 7395408 | Parallel execution processor and instruction assigning making use of group number in processing elements | Takeshi Tanaka, Satoshi Takashima, Hideshi Nishida, Tokuzo Kiyohara | 2008-07-01 |
| 7386707 | Processor and program execution method capable of efficient program execution | Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota +5 more | 2008-06-10 |
| 7315934 | Data processor and program for processing a data matrix | Hiroyuki Morishita, Atsushi Ito, Satoshi Takashima, Hideshi Nishida, Tokuzo Kiyohara +2 more | 2008-01-01 |
| 7236948 | Foot shape information distributing network system | Masaaki Mochimaru, Makiko Kouchi, Tsuneaki Utsumi | 2007-06-26 |
| 7079583 | Media processing apparatus which operates at high efficiency | Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara | 2006-07-18 |
| 7020787 | Microprocessor | Satoshi Takashima, Hideshi Nishida, Tokuzo Kiyohara | 2006-03-28 |
| 6901454 | Circuit group control system | Nobuo Higaki, Tetsuya Tanaka, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara +1 more | 2005-05-31 |
| 6829302 | Pixel calculating device | Hiroyuki Morishita, Kosuke Yoshioka, Hideshi Nishida, Makoto Hirai, Ryuji Matsuura +2 more | 2004-12-07 |
| 6809777 | Pixel calculating device | Hiroyuki Oka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara, Makoto Hirai +3 more | 2004-10-26 |
| 6340973 | Memory control unit and memory control method and medium containing program for realizing the same | Toshiyuki Ochiai, Yosuke Furukawa, Yutaka Tanaka, Makoto Hirai, Tokuzo Kiyohara +1 more | 2002-01-22 |
| 6310921 | Media processing apparatus which operates at high efficiency | Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara | 2001-10-30 |
| 6212236 | Image decoding apparatus | Hideshi Nishida, Makoto Hirai, Tokuzo Kiyohara | 2001-04-03 |
| 6105127 | Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream | Tokuzo Kiyohara, Kousuke Yoshioka | 2000-08-15 |
| 6075899 | Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system | Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara | 2000-06-13 |
| 5546593 | Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream | Hiroaki Hirata | 1996-08-13 |