RJ

Romain Jaillet

SS Stmicroelectronics (Tours) Sas: 2 patents #61 of 132Top 50%
Overall (All Time): #1,823,153 of 4,157,543Top 45%
2
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11784104 Method of forming electronic chip package having a conductive layer between a chip and a support Olivier Ory 2023-10-10
11158556 Electronic chip package having a support and a conductive layer on the support Olivier Ory 2021-10-26