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Method, device and article to test digital circuits |
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Method for managing the operation of a test mode of a logic component with restoration of the pre-test state |
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Onboard Kahn network type system comprising a plurality of source and destination actors in order to manage buffer memories based on tokens |
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Method and apparatus for compression and decompression of an executable code with a RISC processor |
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Processes and devices for compression and decompression of executable code by a microprocessor with RISC architecture and related system |
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Dual port memory for digital signal processor |
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DSP architecture optimized for memory accesses |
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Process for determining an overflow to the format of the result of an arithmetic operation carried out on two operands |
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