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Memory system and operating method thereof |
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Memory system and operating method thereof |
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Memory device, memory system including the same and operation method of the memory system |
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Semiconductor memory device |
Choung Ki SONG, Tae Woo Kwon |
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Semiconductor memory apparatus and test method using the same |
Choung Ki SONG, Sang Sic Yoon, Yong Gu Kang, Gyung Tae Kim |
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Determining and using dynamic voltage scaling mode |
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2012-11-27 |
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Circuit for generating negative voltage and semiconductor memory apparatus using the same |
Yeon Uk Kim |
2011-05-17 |
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Test circuit for performing multiple test modes |
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2011-02-15 |
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Apparatus for generating internal voltage in semiconductor integrated circuit |
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2010-12-14 |
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Test circuit for performing multiple test modes |
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2010-11-23 |
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Apparatus and method of generating clock signal of semiconductor memory |
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2010-11-09 |
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Semiconductor package capable of performing various tests and method of testing the same |
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2010-11-09 |
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Semiconductor memory device voltage generating circuit for avoiding leakage currents of parasitic diodes |
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2010-08-03 |
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Negative voltage generating device |
Yeon Uk Kim |
2010-07-06 |
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Power-up signal generating apparatus |
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2007-05-01 |
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Semiconductor memory device with mode register and method for controlling deep power down mode therein |
Kie Bong Koo |
2004-06-01 |
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Redundancy circuit of semiconductor memory device |
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2003-10-28 |
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Power voltage driver circuit for low power operation mode |
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2003-04-08 |
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Boosting circuit for high voltage operation |
Seung Han Ok |
2003-02-11 |
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Refresh control circuit |
Ji-Bum Kim |
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Input/output voltage detection type substrate voltage generation circuit |
— |
1999-09-14 |