| 12333351 |
Synchronization of processing elements that execute statically scheduled instructions in a machine learning accelerator |
Nishit Shah, Srivathsa Dhruvanarayan |
2025-06-17 |
| 11989581 |
Software managed memory hierarchy |
Nishit Shah |
2024-05-21 |
| 11886981 |
Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions |
Nishit Shah, Srivathsa Dhruvanarayan |
2024-01-30 |
| 11803740 |
Ordering computations of a machine learning network in a machine learning accelerator for efficient memory usage |
Nishit Shah |
2023-10-31 |
| 11782757 |
Scheduling off-chip memory access for programs with predictable execution |
— |
2023-10-10 |
| 11734605 |
Allocating computations of a machine learning network in a machine learning accelerator |
Nishit Shah |
2023-08-22 |
| 11734549 |
Avoiding data routing conflicts in a machine learning accelerator |
Nishit Shah |
2023-08-22 |
| 11586894 |
Ordering computations of a machine learning network in a machine learning accelerator for efficient memory usage |
Nishit Shah |
2023-02-21 |
| 11403519 |
Machine learning network implemented by statically scheduled instructions, with system-on-chip |
Nishit Shah, Srivathsa Dhruvanarayan, Moenes Zaher Iskarous, Kavitha Prasad, Yogesh Laxmikant Chobe +2 more |
2022-08-02 |
| 11354570 |
Machine learning network implemented by statically scheduled instructions, with MLA chip |
Nishit Shah, Srivathsa Dhruvanarayan, Moenes Zaher Iskarous, Kavitha Prasad, Yogesh Laxmikant Chobe +2 more |
2022-06-07 |
| 11321607 |
Machine learning network implemented by statically scheduled instructions, with compiler |
Nishit Shah, Srivathsa Dhruvanarayan, Moenes Zaher Iskarous, Kavitha Prasad, Yogesh Laxmikant Chobe +2 more |
2022-05-03 |