PV

Paul G. G. VanLoon

SI Siliconix Incorporated: 1 patents #74 of 125Top 60%
📍 San Jose, CA: #22,480 of 32,062 inventorsTop 75%
🗺 California: #247,236 of 386,348 inventorsTop 65%
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1
Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
4203126 CMOS structure and method utilizing retarded electric field for minimum latch-up Ernest W. Yim 1980-05-13