Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7165193 | Efficient memory allocation scheme for data collection | Joey Chen, Thuji Simon Lin, Anders Hebsgaard | 2007-01-16 |
| 6836861 | Efficient memory allocation scheme for data collection | Joey Chen, Thuji Simon Lin, Anders Hebsgaard | 2004-12-28 |
| 5852617 | Jtag testing of buses using plug-in cards with Jtag logic mounted thereon | — | 1998-12-22 |
| 5826043 | Docking station with serially accessed memory that is powered by a portable computer for identifying the docking station | Michael G. Smith | 1998-10-20 |
| 5815673 | Method and apparatus for reducing latency time on an interface by overlapping transmitted packets | — | 1998-09-29 |
| 5805609 | Method and apparatus for testing a megacell in an ASIC using JTAG | — | 1998-09-08 |
| 5764966 | Method and apparatus for reducing cumulative time delay in synchronizing transfer of buffered data between two mutually asynchronous buses | — | 1998-06-09 |
| 5731715 | Glitch-free clock enable circuit | — | 1998-03-24 |
| 5666494 | Queue management mechanism which allows entries to be processed in any order | — | 1997-09-09 |
| 5654929 | Refresh strategy for DRAMs | — | 1997-08-05 |
| 5648973 | I/O toggle test method using JTAG | — | 1997-07-15 |
| 5638534 | Memory controller which executes read and write commands out of order | — | 1997-06-10 |
| 5631912 | High impedance test mode for JTAG | — | 1997-05-20 |
| 5630110 | Method and apparatus for enhancing performance of a processor | — | 1997-05-13 |
| 5537062 | Glitch-free clock enable circuit | — | 1996-07-16 |
| 5324996 | Floating fault tolerant input buffer circuit | — | 1994-06-28 |