Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| D545009 | Dishwasher | Yun Tae Jung, So Jin Park, Hyeon Geun Oh | 2007-06-19 |
| 7117514 | Multi-tuner television receiving apparatus and method of restricting the viewing | — | 2006-10-03 |
| D529242 | Washing machine | Young Soo Ha, Young Il Kim, Ho Il Jeon | 2006-09-26 |
| D528712 | Washing machine | Young Soo Ha, Young Il Kim, Ho Il Jeon | 2006-09-19 |
| D528713 | Washing machine | Young Soo Ha, Young Il Kim, Ho Il Jeon | 2006-09-19 |
| 7062148 | Apparatus and method of controlling playback according to program ratings | — | 2006-06-13 |
| 6741506 | Reduced power bit line selection in memory circuits | — | 2004-05-25 |
| 6687169 | Semiconductor memory device for providing address access time and data access time at a high speed | Je-Hun Ryu | 2004-02-03 |
| 6580651 | Reduced power bit line selection in memory circuits | — | 2003-06-17 |
| 6556488 | Delay locked loop for use in semiconductor memory device | — | 2003-04-29 |
| 6538956 | Semiconductor memory device for providing address access time and data access time at a high speed | Je-Hun Ryu | 2003-03-25 |
| 6489822 | Delay locked loop with delay control unit for noise elimination | — | 2002-12-03 |
| 6483765 | Semiconductor memory device and bit line connecting method thereof | — | 2002-11-19 |
| 6449674 | Internal command signal generator and method therefor | Mi-Kyung Yun | 2002-09-10 |
| 6445234 | Apparatus and method for accelerating initial lock time of delayed locked loop | Min-Ho Yoon | 2002-09-03 |
| 6392911 | Reduced power bit line selection in memory circuits | — | 2002-05-21 |
| 6314050 | Data strobe buffer in SDRAM | Seung-Hyun Yi | 2001-11-06 |
| 6292420 | Method and device for automatically performing refresh operation in semiconductor memory device | Kang-Yong Kim, Saeng Hwan Kim | 2001-09-18 |
| 6243302 | Apparatus for outputting data using common pull-up/pull-down lines with reduced load | Min-Ho Yoon | 2001-06-05 |
| 6240041 | Signal generator with timing margin by using control signal to control different circuit | Sung-Ho Bae | 2001-05-29 |
| 6229748 | Memory device using one common bus line between address buffer and row predecoder | Je-Hun Ryu | 2001-05-08 |
| 6215710 | Apparatus and method for controlling data strobe signal in DDR SDRAM | Shin Ho Chu | 2001-04-10 |
| 6201760 | Apparatus and method for performing data read operation in DDR SDRAM | Mi-Kyung Yun | 2001-03-13 |
| 6166988 | Semiconductor memory device using one common address bus line between address buffers and column predecoder | Je-Hun Ryu | 2000-12-26 |
| 6008998 | AC/DC power supply circuit | — | 1999-12-28 |