Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9710241 | Apparatus and method for providing instruction for heterogeneous processor | Egger Bernhard, Soo-Jung Ryu, Dong-Hoon Yoo | 2017-07-18 |
| 9405683 | Processor and memory control method for allocating instructions to a cache and a scratch pad memory | Soojung Ryu, Dong-Hoon Yoo, Dong-kwan Suh, Jeongwook Kim, Choon Ki Jang | 2016-08-02 |
| 9342480 | Apparatus and method for generating VLIW, and processor and method for processing VLIW | Bernhard Egger, Soo-Jung Ryu, Dong-Hoon Yoo | 2016-05-17 |
| 9086959 | Apparatus to access multi-bank memory | Woong Seo, Soo-Jung Ryu, Yoon-Jin Kim, Young-Chul Cho, Tae-Wook Oh | 2015-07-21 |
| 9015451 | Processor including a cache and a scratch pad memory and memory control method thereof | Soojung Ryu, Dong-Hoon Yoo, Dong-kwan Suh, Jeongwook Kim, Choon Ki Jang | 2015-04-21 |
| 8768680 | Simulator of multi-core system employing reconfigurable processor cores and method of simulating multi-core system employing reconfigurable processor cores | Young-Chul Cho, Soo-Jung Ryu, Yoon-Jin Kim, Woong Seo, Tae-Wook Oh | 2014-07-01 |
| 8725486 | Apparatus and method for simulating a reconfigurable processor | Tae-Wook Oh, Soo-Jung Ryu, Yoon-Jin Kim, Woong Seo, Young-Chul Cho | 2014-05-13 |
| 8688891 | Memory controller, method of controlling unaligned memory access, and computing apparatus incorporating memory controller | Woong Seo, Soo-Jung Ryu, Yoon-Jin Kim, Young-Chul Cho, Tae-Wook Oh | 2014-04-01 |
| 8677099 | Reconfigurable processor with predicate signal activated operation configuration memory and separate routing configuration memory | Soo-Jung Ryu, Dong-Hoon Yoo, Yeon-Gon Cho, Bernhard Egger, Woong Seo | 2014-03-18 |
| 8601244 | Apparatus and method for generating VLIW, and processor and method for processing VLIW | Bernhard Egger, Soo-Jung Ryu, Dong-Hoon Yoo | 2013-12-03 |
| 8516231 | Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus | Soo-Jung Ryu, Dong-Hoon Yoo, Yeon-Gon Cho, Bernhard Egger | 2013-08-20 |
| 8495345 | Computing apparatus and method of handling interrupt | Dong-Hoon Yoo, Soo-Jung Ryu, Yeon-Gon Cho, Bernhard Egger | 2013-07-23 |
| 8417918 | Reconfigurable processor with designated processing elements and reserved portion of register file for interrupt processing | Bernhard Egger, Dong-Hoon Yoo, Soo-Jung Ryu | 2013-04-09 |
| 8095806 | Method of power simulation and power simulator | Dong-kwan Suh, Soojung Ryu, Dong-Hoon Yoo | 2012-01-10 |
| 8078835 | Reconfigurable array processor for floating-point operations | Hoon Mo Yang, Man Hwee Jo, Ki Young Choi | 2011-12-13 |
| 8046564 | Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation | Hoon Mo Yang, Man Hwee Jo, Ki Young Choi | 2011-10-25 |
| 7836277 | Pre-tracing instructions for CGA coupled processor in inactive mode for execution upon switch to active mode and continuing pre-fetching cache miss instructions | Dong-Hoon Yoo, Dong-kwan Suh, Soojung Ryu, Jeongwook Kim | 2010-11-16 |