Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5745655 | Chaotic neural circuit and chaotic neural network using the same | Ik-Soo Lee | 1998-04-28 |
| 5613042 | Chaotic recurrent neural network and learning method therefor | Hye-young Tak | 1997-03-18 |
| 5517139 | Non-linear circuit and chaotic neuron circuit using the same | Yil Suk Yang | 1996-05-14 |
| 5471557 | Speech recognition system utilizing a neural network | Soo-Yong LEE | 1995-11-28 |
| 5450528 | Self-learning neural multi-layer network and learning method thereof | Kyung-Hun Lee | 1995-09-12 |
| 5448682 | Programmable multilayer neural network | Kyung-Hun Lee | 1995-09-05 |
| 5442209 | Synapse MOS transistor | — | 1995-08-15 |
| 5347613 | MOS multi-layer neural network including a plurality of hidden layers interposed between synapse groups for performing pattern recognition | Hyo Jin Han | 1994-09-13 |
| 5293458 | MOS Multi-layer neural network and its design method | Sin-jin Kim | 1994-03-08 |
| 5260706 | Priority encoder | — | 1993-11-09 |
| 5239597 | Nearest neighbor dither image processing circuit | Ji H. Yeo | 1993-08-24 |
| 5177746 | Error correction circuit using a design based on a neural network model | — | 1993-01-05 |
| 5166938 | Error correction circuit using a design based on a neural network model comprising an encoder portion and a decoder portion | — | 1992-11-24 |
| 5155699 | Divider using neural network | Sin-jin Kim, Tae Hun Kim | 1992-10-13 |
| 5130944 | Divider circuit adopting a neural network architecture to increase division processing speed and reduce hardware components | Sin-jin Kim, Tae Hun Kim | 1992-07-14 |
| 5086405 | Floating point adder circuit using neural network | Seung-yeob Paek | 1992-02-04 |