Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12425275 | Hybrid source-series termination driver with constant output swing | Minsoo Choi, Hiep T. Pham, Hyojun Kim | 2025-09-23 |
| 11431344 | Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition | Yongrong Zuo, Wanghua Wu | 2022-08-30 |
| 11354476 | Simulation method of an electron device | Nobuyuki Sano, Hiroshi Watanabe | 2022-06-07 |
| 11233627 | System and method for providing fast-settling quadrature detection and correction | Zhiqiang Huang, Hiep Pham | 2022-01-25 |
| 11175633 | System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL) | Ronghua Ni | 2021-11-16 |
| 11115005 | Ring voltage controlled oscillator (VCO) startup helper circuit | Xiong Liu | 2021-09-07 |
| 11063599 | Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition | Yongrong Zuo, Wanghua Wu | 2021-07-13 |
| 11050428 | Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit | Zhiqiang Huang, Hiep Pham | 2021-06-29 |
| 10996634 | System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL) | Ronghua Ni | 2021-05-04 |
| 10965297 | Sigma-delta modulation quantization error reduction technique for fractional-N phase-locked loop (PLL) | Wanghua Wu | 2021-03-30 |
| 10917078 | System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL) | Wanghua Wu | 2021-02-09 |
| 10841072 | System and method for providing fast-settling quadrature detection and correction | Zhiqiang Huang, Hiep Pham | 2020-11-17 |
| 10812088 | Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit | Zhiqiang Huang, Hiep Pham | 2020-10-20 |
| 10623010 | System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to- digital converter (TDC) | Wing Fai Loke | 2020-04-14 |
| 10581418 | System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL) | Wanghua Wu | 2020-03-03 |
| 10418981 | System and method for calibrating pulse width and delay | Wing Fai Loke | 2019-09-17 |
| 10009036 | System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to-digital converter (TDC) | Wing Fai Loke | 2018-06-26 |
| 9746832 | System and method for time-to-digital converter fine-conversion using analog-to-digital converter (ADC) | — | 2017-08-29 |
| 9595915 | Fine tuning control apparatus and method | Wing Fai Loke, Sunghwan Kim | 2017-03-14 |
| 9379662 | System and method using temperature tracking for a controlled oscillator | Wing Fai Loke | 2016-06-28 |
| 9356555 | Fine tuning control for a digitally controlled oscillator | Wing Fai Loke, Sunghwan Kim | 2016-05-31 |
| 9240914 | Communication system with frequency synthesis mechanism and method of operation thereof | — | 2016-01-19 |
| 9219484 | Reference clock compensation for fractional-N phase lock loops (PLLS) | — | 2015-12-22 |
| 8970421 | High resolution sampling-based time to digital converter | Xiang Gao, Chi-Hung Lin, Li Lin | 2015-03-03 |
| 8717074 | Reference clock compensation for fractional-N phase lock loops (PLLs) | — | 2014-05-06 |