Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8447961 | Mechanism for efficient implementation of software pipelined loops in VLIW processors | Anindya Saha, Manish Kumar, Hemant Mallapur, Viji Rajangam | 2013-05-21 |
| 8255780 | Scalable VLIW processor for high-speed viterbi and trellis coded modulation decoding | Anindya Saha, Hemant Mallapur, Smitha Banavikal Math Veerabhadresh | 2012-08-28 |