ST

Shigemitsu Tahara

RT Renesas Technology: 2 patents #1,374 of 3,337Top 45%
📍 Chitose, JP: #18 of 51 inventorsTop 40%
Overall (All Time): #2,173,093 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7109779 Semiconductor integrated circuit and a burn-in method thereof Daisuke Katagiri, Takeshi Shimanuki, Masashi Oshiba 2006-09-19
6777997 Semiconductor integrated circuit and a burn-in method thereof Daisuke Katagiri, Takeshi Shimanuki, Masashi Oshiba 2004-08-17