Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8108809 | Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit | Ken Saito, Yoshio Inoue | 2012-01-31 |
| 7418688 | Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit | Ken Saito, Yoshio Inoue | 2008-08-26 |