KI

Kazuyuki Irie

RE Renesas Electronics: 4 patents #1,016 of 4,529Top 25%
NE Nec Electronics: 2 patents #384 of 1,789Top 25%
Overall (All Time): #857,011 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
8751991 Layout method, layout system, and non-transitory computer readable medium storing layout program of semiconductor integrated circuit 2014-06-10
8312403 Method of achieving convergence of hold time error, device and program therefor 2012-11-13
8164374 Clock gating circuit having a selector that selects one of a control signal and a scan signal 2012-04-24
7919981 Integrated circuit design based on scan design technology 2011-04-05
6901567 Method of performing timing-driven layout 2005-05-31
6584607 Method of performing timing-driven layout 2003-06-24