HY

Hirofumi Yonetoku

RE Renesas Electronics: 2 patents #1,855 of 4,529Top 45%
NE Nec: 1 patents #7,889 of 14,502Top 55%
NE Nec Electronics: 1 patents #715 of 1,789Top 40%
Overall (All Time): #1,204,002 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
9341674 Scan test circuit, test pattern generation control circuit, and scan test control method Norihiro Yamada 2016-05-17
9081058 Scan test circuit, test pattern generation control circuit, and scan test control method Norihiro Yamada 2015-07-14
6836867 Method of generating a pattern for testing a logic circuit and apparatus for doing the same 2004-12-28
5719881 Test pattern generating apparatus and method 1998-02-17