| 5652886 |
System for loading a boot program into an initially blank programmable memory of a microprocessor using state machine and serial bus |
Mark A. Foss, Edward J. Kysar, III, Edward M. Oscarson, Leonard Spain, Michael C. Crisafulli |
1997-07-29 |
| 5617544 |
Interface having receive and transmit message label memories for providing communication between a host computer and a bus |
Steven A. Avritch, Geoffrey T. Blackwell, Andrew M. MacKay |
1997-04-01 |
| 5202679 |
Mid-value signal selection system |
Steven A. Avritch |
1993-04-13 |
| 5128943 |
Independent backup mode transfer and mechanism for digital control computers |
Edward M. Oscarson |
1992-07-07 |
| 5093910 |
Serial data transmission between redundant channels |
Daniel G. Binnall |
1992-03-03 |
| 4980824 |
Event driven executive |
Robert E. Collins, John Cheetham, Smith William Cornwell |
1990-12-25 |
| 4959782 |
Access arbitration for an input-output controller |
Daniel G. Binnall |
1990-09-25 |
| 4933836 |
n-Dimensional modular multiprocessor lattice architecture |
Robert E. Collins, Daniel G. Binnall |
1990-06-12 |
| 4771427 |
Equalization in redundant channels |
Robert E. Collins, Donald F. Cominelli, Richard D. O'Neill |
1988-09-13 |
| 4727549 |
Watchdog activity monitor (WAM) for use wth high coverage processor self-test |
Richard W. Crosset, III, Richard E. Versailles |
1988-02-23 |
| 4696019 |
Multi-channel clock synchronizer |
Edward M. Oscarson, David J. Vosgien |
1987-09-22 |
| 4635254 |
Coherent interface with wraparound receive memory |
Matthew Blaha |
1987-01-06 |
| 4625307 |
Apparatus for interfacing between at least one channel and at least one bus |
Matthew Blaha |
1986-11-25 |
| 4623997 |
Coherent interface with wraparound receive and transmit memories |
— |
1986-11-18 |
