Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11221667 | Dynamic voltage selection for a single power rail in a multi-core domain | Venkatesh RAVIPATI, Venkata Biswanath Devarasetty, Nirav Narendra Desai, Lakshmi Narayana PANUKU, Kumar Kanti Ghosh +2 more | 2022-01-11 |
| 10522108 | Optimized histogram reads for efficient display post processing and improved power gains | Venkata Nagarjuna Sravan Kumar DEEPALA, Raviteja Tamatam, Jayant Shekhar | 2019-12-31 |
| 10108449 | Work item management among worker threads of a computing device | Krishna V.S.S.S.R. Vanka, Krishna Gogineni, Murali Dhulipala | 2018-10-23 |
| 9959075 | System and method for flush power aware low power mode control in a portable computing device | KRISHNA VSSSR VANKA, Narasimhan Agaram | 2018-05-01 |
| 9733694 | Apparatus, system and method for dynamic power management across heterogeneous processors in a shared power domain | Hee Jun Park, KRISHNA VSSSR VANKA, Shirish Kumar Agarwal, Shih-Hsin Jason Hu | 2017-08-15 |
| 9717051 | Proactive control of hardware based upon monitored processing | Krishna V.S.S.S.R. Vanka, Shirish Kumar Agarwal, Nikhil Kumar Kansal | 2017-07-25 |
| 9697124 | Systems and methods for providing dynamic cache extension in a multi-cluster heterogeneous processor architecture | Hee Jun Park, KRISHNA VSSSR VANKA, Shirish Kumar Agarwal, Ashvinkumar Namjoshi, Harshad Bhutada | 2017-07-04 |
| 9678809 | System and method for providing dynamic clock and voltage scaling (DCVS) aware interprocessor communication | KRISHNA VSSSR VANKA, Shirish Kumar Agarwal | 2017-06-13 |
| 9671857 | Apparatus, system and method for dynamic power management across heterogeneous processors in a shared power domain | KRISHNA VSSSR VANKA, Hee Jun Park, Shirish Kumar Agarwal | 2017-06-06 |
| 9652022 | System and method for providing dynamic quality of service levels based on coprocessor operation | Asutosh Das, KRISHNA VSSSR VANKA, Sujit Reddy Thumma | 2017-05-16 |
| 9619014 | Suspend and resume timeline optimization for application processor | Krishna V.S.S.S.R. Vanka, Murali Nalajala, Shirish Kumar Agarwal, Nikhil Kumar Kansal | 2017-04-11 |
| 9244747 | System and method for providing dynamic clock and voltage scaling (DCVS) aware interprocessor communication | KRISHNA VSSSR VANKA, Shirish Kumar Agarwal | 2016-01-26 |