Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11146306 | Isolation among I/O ports | Chao Lu, William W. Si | 2021-10-12 |
| 10884449 | Wideband LO signal generation | Alireza Khalili, Mohammad Emadi, Ali Mostajeran | 2021-01-05 |
| 9804664 | Adaptive control of RF low power modes in a multi-rate wireless system using MCS value | Sandip Homchaudhuri, Paul J. Husted, MeeLan Lee, Srenik Mehta, Kai Shi +7 more | 2017-10-31 |
| 9794091 | Agile radar detection for wireless communications | Tevfik Yucek, Felix Bitterli, Lalitkumar Nathawad, James Michael Gardner, Christopher Pisz +4 more | 2017-10-17 |
| 9781673 | Adaptive control of RF low power modes in a multi-rate wireless system using device mode | Sandip Homchaudhuri, Paul J. Husted, MeeLan Lee, Srenik Mehta, Kai Shi +7 more | 2017-10-03 |
| 9531528 | Multi-chip TX beamforming for per-packet switching without LO phase alignment circuitry | Hyunsik Park | 2016-12-27 |
| 9401801 | Multi-chip TX beamforming for per-packet switching with reduced LO leakage | Hyunsik Park, Lalitkumar Nathawad | 2016-07-26 |
| 9210535 | Systems and methods for active interference cancellation to improve coexistence | Alireza Kheirkhahi, Lalitkumar Nathawad, Ke Gong, Ali Agah | 2015-12-08 |
| 9077445 | Temperature compensated RF peak detector | Yashar Rajavi | 2015-07-07 |
| 8908575 | Methods and systems for calibrating a frequency-division duplexing transceiver | Masoud Zargari | 2014-12-09 |
| 8736329 | Systems and methods for providing duty cycle correction | Yashar Rajavi, Hakan Dogan | 2014-05-27 |
| 8547169 | Programmable noise filtering for bias kickback disturbances | Hakan Dogan | 2013-10-01 |
| 8295845 | Transceiver I/Q mismatch calibration | Bemini Hennadige Janath Peiris | 2012-10-23 |
| 8144811 | Hybrid zero-IF receiver | Paul J. Husted, David J. Weber, Soner Ozgur | 2012-03-27 |
| 7526603 | High-speed low-power CAM-based search engine | Mayur Joshi | 2009-04-28 |
| 7464282 | Apparatus and method for producing dummy data and output clock generator using same | Chaofeng Huang | 2008-12-09 |
| 7089439 | Architecture and method for output clock generation on a high speed memory device | Chaofeng Huang | 2006-08-08 |
| 6975260 | Geometric D/A converter for a delay-locked loop | Chaofeng Huang | 2005-12-13 |
| 6947349 | Apparatus and method for producing an output clock pulse and output clock generator using same | Chaofeng Huang | 2005-09-20 |
| 6941417 | High-speed low-power CAM-based search engine | Mayur Joshi | 2005-09-06 |
| 6891774 | Delay line and output clock generator using same | Chaofeng Huang | 2005-05-10 |
| 6819278 | Geometric D/A converter for a delay-locked loop | Chaofeng Huang | 2004-11-16 |
| 6734815 | Geometric D/A converter for a delay-locked loop | Chaofeng Huang | 2004-05-11 |