Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11264995 | System and method for maintaining local oscillator (LO) phase continuity | Yue-Li Chao, Yiwu Tang, Yunliang Zhu, Dongmin Park | 2022-03-01 |
| 10575279 | Methods and apparatus for a transmit path with frequency hopping phase locked loop | Bhushan Shanti Asuri, Praveen Sampath, Shrenik Patel, Jeremy Darren Dunworth, Lai Kan Leung +2 more | 2020-02-25 |
| 10534025 | Phase frequency detector linearization using switching supply | — | 2020-01-14 |
| 10523272 | Distributed differential interconnect | Madhukar Vallabhaneni, Girish Koppassery, Xinhua Chen | 2019-12-31 |
| 10256796 | Master-slave level shifter array architecture with pre-defined power-up states | Shih-Chieh Hsin, Med NARIMAN | 2019-04-09 |
| 10177772 | Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation | Xinhua Chen, Frederic Bossu, Yiwu Tang | 2019-01-08 |
| 10116315 | System-on-a-chip clock phase management using fractional-N PLLs | Frederic Bossu | 2018-10-30 |
| 9998129 | PLL post divider phase continuity | Jianyun Hu, Animesh Paul, Xinhua Chen, Frederic Bossu | 2018-06-12 |
| 9973182 | Re-timing based clock generation and residual sideband (RSB) enhancement circuit | Animesh Paul, Xinhua Chen, Ravi Sridhara | 2018-05-15 |
| 9893875 | Phase continuity technique for frequency synthesis | Marco Zanuso, Mohammad Elbadry, Tsai-Pi Hung, Ravi Sridhara, Francesco Gatta | 2018-02-13 |
| 9864341 | Time-to-digital conversion with latch-based ring | — | 2018-01-09 |
| 9584184 | Unified front-end receiver interface for accommodating incoming signals via AC-coupling or DC-coupling | Miao Li, Xiaohua Kong, Wei-Chung Wang | 2017-02-28 |
| 9520887 | Glitch free bandwidth-switching scheme for an analog phase-locked loop (PLL) | Jong Min Park, Lai Kan Leung, Yiwu Tang | 2016-12-13 |
| 9176511 | Band-gap current repeater | Nam V. Dang, Rajeev Jain, Terrence Brian Remple, Mong Chit Wong | 2015-11-03 |
| 8970254 | Systems and methods for frequency detection | Glenn A. Murphy, Xiaohua Kong, William Knox Ladd | 2015-03-03 |
| 8928365 | Methods and devices for matching transmission line characteristics using stacked metal oxide semiconductor (MOS) transistors | Miao Li, Yan-Yan Hu, Xiaoliang Bai, Jing X. Kang | 2015-01-06 |
| 8839020 | Dual mode clock/data recovery circuit | Nam V. Dang, Xiaohua Kong, Zhi Zhu, Tirdad Sowlati, Behnam Amelifard | 2014-09-16 |
| 8830001 | Low power all digital PLL architecture | Robert Bogdan Staszewski | 2014-09-09 |
| 8497723 | Low-hysteresis high-speed differential sampler | — | 2013-07-30 |
| 8461896 | Compensating for wander in AC coupling data interface | — | 2013-06-11 |
| 8319579 | Passive filter and AC coupler receiver interface | Bruce A. Doyle, Emerson S. Fang | 2012-11-27 |
| 8306174 | Fractional interpolative timing advance and retard control in a transceiver | Thomas Murphy, Khurram Waheed, Roman Staszewski | 2012-11-06 |
| 8204107 | Bandwidth reduction mechanism for polar modulation | Robert Bogdan Staszewski, Khurram Waheed | 2012-06-19 |
| 8045662 | Binary ripple counter sampling with adjustable delays | Robert Bogdan Staszewski | 2011-10-25 |
| 8014480 | Zero-delay serial communications circuitry for serial interconnects | Qingjin Du, Tad Kwasniewski, Rakesh Patel | 2011-09-06 |