Issued Patents All Time
Showing 26–50 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10199289 | Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2019-02-05 |
| 10199290 | Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2019-02-05 |
| 10199294 | Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2019-02-05 |
| 10109539 | Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-10-23 |
| 10096530 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-10-09 |
| 10096529 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-10-09 |
| 9984944 | Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-05-29 |
| 9953889 | Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-04-24 |
| 9947601 | Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-04-17 |
| 9929136 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-27 |
| 9929063 | Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-27 |
| 9922890 | Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-20 |
| 9922968 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-20 |
| 9911669 | Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-06 |
| 9911670 | Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-06 |
| 9911649 | Process for making and using mesh-style NCEM pads | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-06 |
| 9911668 | Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-03-06 |
| 9905487 | Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-02-27 |
| 9905553 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-02-27 |
| 9899276 | Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-02-20 |
| 9881843 | Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-01-30 |
| 9870962 | Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-01-16 |
| 9870966 | Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of AACNT-TS via opens | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-01-16 |
| 9871028 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-01-16 |
| 9865583 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells | Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2018-01-09 |