Issued Patents All Time
Showing 26–50 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10199294 | Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2019-02-05 |
| 10109539 | Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-10-23 |
| 10102330 | Method for automatically determining proposed standard cell design conformance based upon template constraints | Elizabeth Lagnese | 2018-10-16 |
| 10096530 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-10-09 |
| 10096529 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-10-09 |
| 9984970 | Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs | — | 2018-05-29 |
| 9984944 | Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-05-29 |
| 9953889 | Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-04-24 |
| 9947601 | Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-04-17 |
| 9929063 | Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-27 |
| 9929136 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-27 |
| 9922968 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-20 |
| 9922890 | Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-20 |
| 9911668 | Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-06 |
| 9911649 | Process for making and using mesh-style NCEM pads | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-06 |
| 9911669 | Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-06 |
| 9911670 | Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-03-06 |
| 9905553 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-02-27 |
| 9905487 | Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-02-27 |
| 9899276 | Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-02-20 |
| 9881843 | Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-01-30 |
| 9871028 | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-01-16 |
| 9870966 | Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of AACNT-TS via opens | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-01-16 |
| 9870962 | Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +20 more | 2018-01-16 |
| 9870441 | Snap-to valid pattern system and method | Elizabeth Lagnese | 2018-01-16 |