Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High-throughput low-latency erasure error correction in an integrated circuit

High-throughput low-latency erasure error correction in an integrated circuit

US Patent 9985654 · Granted May 29, 2018

Estimated economic value: $17,200,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Authentication system having pipelined processing2025
Detection method, apparatus and system2025
Device of detecting ray dose adaptable for coupling with terminal and method of 2025
Systems and methods to extract beamforming parameters at a radio unit (RU) of a 2024
System and method for determining bit types for polar encoding and decoding2021
Human body security inspection apparatus and method of operating the same and fi2021
Collimating device and ray inspection device2019
Ray beam guiding device and ray inspection apparatus having the same2019
Safety inspection apparatus2019
Human body security inspection apparatus2018
Montgomery multiplication devices2018
Mobile back scattering imaging security inspection apparatus and method2017