Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Substrate noise isolation structures for semiconductor devices

Substrate noise isolation structures for semiconductor devices

US Patent 9923051 · Granted Mar 20, 2018

Estimated economic value: $101,272,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Chip package with integrated off-die inductor2025
Chip package with integrated off-die inductor2025
Method and system for processing intracranial large vessel image, electronic dev2025
Regionally integrated emergency stroke unit2025
Opposite-facing interleaved transformer design2024
Opposite-facing interleaved transformer design2024
Integrated circuit chip testing interface with reduced signal wires2024
Inductor design in active 3D stacking technology2021
Inductor design in active 3D stacking technology2021
Systems and methods for providing capacitor structures in an integrated circuit2020
Systems and methods for providing capacitor structures in an integrated circuit2020
Systems providing interposer structures2020