Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing

Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing

US Patent 9922866 · Granted Mar 20, 2018

Estimated economic value: $2,525,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Reference markers adjacent to a cavity in a photonics chip2025
Cladding structure in the back end of line of photonics chips2025
Conductive oxide diffusion barrier for laser crystallization2025
Aluminum oxide protected lithium metal tunable 3D silicon batteries2025
Waveguide escalators for a photonics chip2025
Energy storage method using aluminum oxide protected lithium metal tunable 3D si2025
Energy storage method using aluminum oxide protected lithium metal tunable 3D si2025
Vertical silicon Josephson Junction device for qubit applications2025
Vertical silicon Josephson Junction device for qubit applications2025
Crossbar memory array in back end of line2025
Lithium-ion battery with thin crystalline anode and methods of making same2025
Crossbar memory array in back end of line with crystallization front2025