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Home › Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device

Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device

US Patent 9881664 · Granted Jan 30, 2018

Estimated economic value: $8,633,000 ⓘ

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