{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Memory architecture and cell design employing two access transistors", "item": "https://www.patentleaderboard.com/patent/9875795"}]}
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Home › Memory architecture and cell design employing two access transistors

Memory architecture and cell design employing two access transistors

US Patent 9875795 · Granted Jan 23, 2018

Estimated economic value: $24,273,000 ⓘ

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