Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Floating-gate transistor array for performing weighted sum computation

Floating-gate transistor array for performing weighted sum computation

US Patent 9760533 · Granted Sep 12, 2017

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and methods for mixed-signal computing2025
System and methods for mixed-signal computing2025
Systems and methods for predicted total loss based on image analysis and point o2025
Systems and methods for predicted total loss determinations based on image analy2025
Systems and methods for implementing an intelligence processing computing archit2025
Systems and methods for mapping matrix calculations to a matrix multiply acceler2025
Systems and methods for mapping matrix calculations to a matrix multiply acceler2025
Ultra-low power readout circuit with high-voltage bias generation for MEMS accel2025
Ultra-low power readout circuit with high-voltage bias generation for MEMS accel2025
Systems and methods for intelligently buffer tracking for optimized dataflow wit2025
Systems and methods for enhancing inferential accuracy of an artificial neural n2025
Systems and methods for implementing an intelligence processing computing archit2024