Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method to optimize STT-MRAM size and write error rate

Apparatus and method to optimize STT-MRAM size and write error rate

US Patent 9711215 · Granted Jul 18, 2017

Estimated economic value: $6,909,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Ferroelectrically modulated spin orbit logic device2025
Ferroelectrically modulated spin orbit logic device2025
Doped polar layers and semiconductor device incorporating same2025
Asynchronous carry-ripple adder with majority or minority gates2025
Differentially programmable magnetic tunnel junction device and system including2025
Differentially programmable magnetic tunnel junction device and system including2025
Perovskite-based magnetoelectric spin-orbit logic devices2025
Perovskite-based magnetoelectric spin-orbit logic devices2025
Perovskite-based magnetoelectric spin-orbit logic devices2025
Fine-grained disaggregated server architecture2025
Integrating embedded memory with logic interconnects2025
Method of forming capacitors through wafer bonding2025