Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Compact logic evaluation gates using null convention

Compact logic evaluation gates using null convention

US Patent 9692419 · Granted Jun 27, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Computer architecture with disaggregated memory and high-bandwidth communication2025
Processor cluster address generation2025
Computer architecture with disaggregated memory and high-bandwidth communication2024
Computer architecture with disaggregated memory and high-bandwidth communication2024
Processor cluster address generation2024
Multidimensional address generation for direct memory access2021
Data flow graph computation using exceptions2021
Methods and apparatus for upgrading set top box devices without the loss of stor2019
Translating instructions in a speculative processor2018
Vascular occlusion devices2017
Injection of supplemental computer instructions2016
Methods and apparatus for upgrading set top box devices without the loss of stor2016