Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Stacked vertical memory array architectures, systems and methods

Stacked vertical memory array architectures, systems and methods

US Patent 9672917 · Granted Jun 6, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Channel pre-charge process in a memory device2025
Three-dimensional nor array and method of making the same2025
Compute in memory three-dimensional non-volatile nor memory for neural networks2025
Configurable capacitors with 3D non-volatile array2025
Field effect transistors with gate fins and method of making the same2025
Preparation method for bio-based nucleating agent for poly(ethylene furandicarbo2025
Electric socket2024
Memory device including mixed oxide charge trapping materials and methods for fo2024
Preventing erase disturb in NAND2024
Three dimensional memory device containing dummy word lines and p-n junction at 2024
Socket2024
Socket2024