Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for making semiconductor device with filled gate line end recesses

Method for making semiconductor device with filled gate line end recesses

US Patent 9653579 · Granted May 16, 2017

Estimated economic value: $8,727,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

TSV and backside power distribution structure2025
Wraparound contact with reduced distance to channel2025
Nanowire source/drain formation for nanosheet device2025
Local enlarged via-to-backside power rail2025
Skip-level TSV with hybrid dielectric scheme for backside power delivery2025
Dual structured buried rail2025
Method and structure of forming independent contact for staggered CFET2025
Strain generation and anchoring in gate-all-around field effect transistors2025
Buried power rail with robust connection to a wrap around contact2025
Formation of trench silicide source or drain contacts without gate damage2025
Isolation rail between backside power rails2025
Decoupling capacitance in backside interconnect2025