Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers

Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers

US Patent 9620497 · Granted Apr 11, 2017

Estimated economic value: $2,654,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electronically programmable fuse with heating transistors2025
Substrate-less lateral diode integrated circuit structures2025
Vertically integrated SCR structure with SOI-based raised trigger element2025
Electrostatic discharge protection devices2025
Electrostatic discharge protection devices including a silicon-controlled rectif2025
Gate-all-around integrated circuit structures having devices with channel-to-sub2025
Substrate-less silicon controlled rectifier (SCR) integrated circuit structures2025
Substrate-free integrated circuit structures2025
Gate-all-around integrated circuit structures having devices with source/drain-t2025
Integrated circuit structure with diode over lateral bipolar transistor2025
Vertically stacked diode-trigger silicon controlled rectifier2024
Fin-based and bipolar electrostatic discharge devices2024