Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Bias circuits and methods for depletion mode semiconductor devices

Bias circuits and methods for depletion mode semiconductor devices

US Patent 9595928 · Granted Mar 14, 2017

Estimated economic value: $3,505,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High electron mobility transistors and power amplifiers including said transisto2023
High electron mobility transistors and power amplifiers including said transisto2021
Method and system for signal emulation2013
Method and system for signal emulation2010
Method and system for automatic control in an interference cancellation device2010
High isolation RF power amplifier with self-bias attenuator2001
Method of fabricating Group III-V compound semiconductor devices using selective1999
Method of fabricating group III-V compound1994