{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Instruction and logic for accelerated compressed data decoding", "item": "https://www.patentleaderboard.com/patent/9564917"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Instruction and logic for accelerated compressed data decoding

Instruction and logic for accelerated compressed data decoding

US Patent 9564917 · Granted Feb 7, 2017

Estimated economic value: $9,424,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Side-channel resistant multiplicatively masked encryption engine with zero-value2025
Pixel block encoder capable of jointly encoding pixel channels2025
Fine-grained bitcoin engine deactivation for yield recovery, performance, and/or2025
Fine-grained bitcoin engine deactivation for yield recovery, performance, and/or2025
Technologies for memory and I/O efficient operations on homomorphically encrypte2025
Technologies for memory and I/O efficient operations on homomorphically encrypte2025
Tamper detection and prevention in computer systems having one-time programmable2025
Instructions and logic to perform floating point and integer operations for mach2025
ROM instruction authentication and integrity verification for artificial reality2025
Instructions and logic to perform floating point and integer operations for mach2024
Low latency post-quantum signature verification for fast secure-boot2024
Low latency post-quantum signature verification for fast secure-boot2024