Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned quadruple patterning

Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned quadruple patterning

US Patent 9553047 · Granted Jan 24, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor device and method for manufacturing the same2025
Memory device with reduced bending stack2024
Memory device2024
Memory device and manufacturing method thereof2024
Memory device and method of fabricating the same2023
Three-dimensional memory device2023
Memory device2023
Memory device and method of manufacturing the same2023
Semiconductor memory structure and manufacturing method thereof2022
Touch device and manufacturing method thereof2022
Memory device with sub-slits2022
Three-dimensional memory device and manufacturing method thereof2021