Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance

Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance

US Patent 9373165 · Granted Jun 21, 2016

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Prediction and metrology of stochastic photoresist thickness defects2025
Lithography mask repair by simulation of photoresist thickness evolution2024
Process-induced distortion prediction and feedforward and feedback correction of2023
Process-induced distortion prediction and feedforward and feedback correction of2023
Process-induced displacement characterization during semiconductor production2023
Process-induced displacement characterization during semiconductor production2021
Prediction based chucking and lithography control optimization2020
Prediction based chucking and lithography control optimization2020
Generating high resolution images from low resolution images for semiconductor a2020
Patterned wafer geometry measurements for semiconductor process controls2020
Patterned wafer geometry measurements for semiconductor process controls2020
Statistical overlay error prediction for feed forward and feedback correction of2020